1. Field of the Invention
The present invention relates to electrical devices, for example semiconductor integrated circuit devices, having inlaid (xe2x80x9cdamascenexe2x80x9d-type) metallization patterns, for example interconnection lines, etc., and to a method for minimizing, or substantially preventing, deleterious electromigration of the metallic element(s) of the metallization pattern. More specifically, the present invention relates to semiconductor devices comprising copper (Cu) interconnection patterns and is applicable to manufacture of high speed integrated circuits having sub-micron dimensioned design features and high electrical conductivity interconnect structures.
2. Description of Related Art
The present invention relates to a method for forming metal films as part of metallization processing of particular utility in the manufacture of electrical and electronic devices, for example circuit boards and semiconductor integrated circuits, and is especially adapted for use in processing employing xe2x80x9cinlaidxe2x80x9d or xe2x80x9cdamascenexe2x80x9d-type technology.
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized (e.g., 0.18 xcexcm and under), low resistance-capacitance (RC) time constant metallization patterns, particularly wherein the sub-micron-sized metallization features, such as vias, contact areas, lines, etc. require grooves, trenches, and other shaped openings or recesses having very high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon (Si) or, in some instances, gallium arsenide (GaAs), and a plurality of sequentially formed interlayer dielectrics and electrically conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced-apart metallization layers or strata are electrically interconnected by a vertically oriented conductive plug filling a via hole formed in the inter-layer dielectric layer separating the layers or strata, while another conductive plug filling a contact area hole establishes electrical contact with an active device region, such as a source/drain region of a transistor, formed in or on the semiconductor substrate. Conductive lines formed in groove- or trench-like openings in overlying inter-layer dielectrics extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more layers or strata of such metallization in order to satisfy device geometry and microminiaturization requirements.
Electrically conductive films or layers of the type contemplated for use in, for example, xe2x80x9cback-endxe2x80x9d semiconductor manufacturing technology for fabricating devices having multi-level metallization patterns such as described supra, typically comprise a metal such as titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), chromium (Cr), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), copper (Cu) and their alloys. In use, each of the enumerated metals presents advantages as well as problems. For example, Al is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, in addition to being difficult to deposit by lower cost, lower temperature, more rapid xe2x80x9cwetxe2x80x9d type technology such as electrodeposition, step coverage with Al is poor when the metallization features are scaled down to sub-micron size, resulting in decreased reliability of interconnections, high current densities at certain locations, and increased electromigration. In addition, certain low dielectric constant materials, for example polyimides, when employed as dielectric inter-layers, create moisture/bias reliability problems when in contact with Al.
Cu and Cu-based alloys are particularly attractive for use in large scale integration (LSI), very large-scale integration (VLSI), and ultra-large scale (ULSI) semiconductor devices requiring multi-level metallization systems for xe2x80x9cback-endxe2x80x9d processing of the semiconductor wafers on which the devices are based. Cu- and Cu alloy-based metallization systems have very low resistivities, i.e., significantly lower than that of W and even lower than those of previously preferred systems utilizing Al and its alloys, as well as a higher (but not complete) resistance to electromigration. Moreover, Cu and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably Ag and Au. Also, in contrast to Al and the refractory-type metals (e.g., Ti, Ta, and W), Cu and its alloys can be readily deposited at low temperatures in good quality, bright layer form by well-known xe2x80x9cwetxe2x80x9d plating such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
As indicated above, a commonly employed method for forming xe2x80x9cinlaidxe2x80x9d metallization patterns as are required for xe2x80x9cback-endxe2x80x9d metallization processing of semiconductor wafers employs xe2x80x9cdamascenexe2x80x9d-type technology. Generally, in such processing methodology, a recess (i.e., an opening for forming, for example, a via hole, in a dielectric layer for electrically connecting vertically separated metallization layers, or a groove or trench for a metallization line) is created in the dielectric layer by conventional photolithographic and etching techniques, and filled with a selected metal. Any excess metal overfilling the recess and/or extending over the surface of the dielectric layer is then removed by, for example, chemical-mechanical polishing (CMP), wherein a moving pad is biased against the surface to be polished/planarized, with the interposition of a slurry containing abrasive particles (and other ingredients) therebetween.
A variant of the above-described technique, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening comprising a lower contact or via hole section in communication with an upper groove or trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive via plug in electrical contact with a conductive line.
Referring now to FIGS. 1A-1C, schematically shown therein in simplified cross-sectional view, is a conventional damascene-type processing sequence employing relatively low cost, high manufacturing throughput plating and CMP techniques for forming recessed xe2x80x9cback-endxe2x80x9d metallization patterns (illustratively of Cu-based metallurgy but not limited thereto) in a semiconductor device formed in or on a semiconductor wafer substrate 1. As shown in FIG. 1A, the desired arrangement of conductors is defined as a pattern of recesses 2 such as via holes, grooves, trenches, etc. formed (as by conventional photolithographic and etching techniques) in the surface 4 of a dielectric layer 3 (e.g., a silicon oxide and/or nitride or an organic polymeric material) deposited or otherwise formed over the semiconductor substrate 1. Then, as shown in FIG. 1B, a layer of conductive metal 5, for example Cu or Cu-based alloy, is deposited by conventional plating techniques, for example electroless or electroplating techniques, to fill the recesses 2. In order to ensure complete filling of the recesses, the conductive metal 5 is deposited as a blanket (or xe2x80x9coverburdenxe2x80x9d) layer of excess thickness so as to overfill the recesses 2 and cover the upper surface 4 of the dielectric layer 3. Next, as shown in FIG. 1C, the entire excess thickness t of the overburden layer of conductive metal 5 over the surface of the dielectric layer 3 is removed by a CMP process utilizing an alumina (A1203)-based slurry, leaving metal portions 5 in the recesses 2 with their exposed upper surfaces 6 substantially co-planar with the surface 4 of the dielectric layer 3.
The above-described conventional damascene-type process forms inlaid conductors (metal portions 5 ) in the dielectric layer 3 while avoiding problems associated with other types of metallization patterning processing, for example blanket metal layer deposition, followed by photolithographic masking/etching and dielectric gap filling. In addition, such single or dual damascene-type processing can be performed with a variety of other types of substrates, for example printed circuit boards, with and/or without intervening dielectric layers, and with a plurality of metallization levels, i.e., five or more levels.
A problem associated with Cu-based xe2x80x9cback-endxe2x80x9d metallization is the possibility of Cu diffusion into adjacent structures, for example an underlying semiconductor substrate (typically Si) or a dielectric layer, resulting in degradation of semiconductive or insulative properties, as well as poor adhesion of the deposited Cu or Cu alloy layer to various materials employed as dielectric inter-layers, etc. As a consequence of these phenomena associated with Cu-based metallurgy, it is generally necessary to provide an adhesion and/or diffusion barrier layer intermediate the semiconductor substrate and the overlying Cu-based metallization layer (not shown in FIGS. 1A through 1C). Suitable materials for such adhesion/barrier layers include, for example, Ti, W, Cr, Ta, and tantalum nitride (TaN).
Another problem associated with the use of Cu or Cu-based metallurgy for xe2x80x9cback-endxe2x80x9d metallization processing of semiconductor devices, results from the undesirable formation of Cu oxide(s), for example Cu2O, CuO, CuO2, etc., on the planarized Cu or Cu-based alloy surfaces of the inlaid metallization features as a result of oxidation, etc., due to the strong chemical oxidizing agents conventionally included in CMP slurries for enhancing Cu dissolution/removal rates and/or as a result of exposure of the freshly abraded Cu-based surfaces to an oxidizing atmosphere, for example air or oxygen. The thickness of the Cu oxide layer can vary depending upon the particular CMP processing conditions, for example stronger oxidizing agents contained in the CMP slurry result in thicker oxide layers, as does increased duration of exposure of freshly abraded, post CMP Cu surfaces to oxidizing atmospheres, for example air.
Cu oxide-containing layer(s), when formed as described above, disadvantageously increase contact resistance and reduce or prevent adhesion of layers thereto, for example silicon nitride-based capping layers. Moreover, the Cu oxide layers are brittle, increasing the likelihood of circuit disconnect or reduced conductivity due to separation, as by peeling, of the Cu oxide layer from conductor layers in contact therewith. Yet another disadvantage attributable to the presence of Cu oxide at the interface between adjacent electrical conductors results from the rapid diffusion of Cu atoms and/or ions along the oxide layer. The latter characteristic of Cu oxide layers disadvantageously results in enhanced material transport during electrical current flow and thus increases the electromigration of Cu atoms and/or ions along Cu-based conductor lines.
Electromigration occurs in extended runs or lengths of metal conductor lines carrying significant currents. According to a conventional theory for explaining the mechanism of electromigration, the current flow within the conductor line can be sufficient to result in movement of Cu atoms and/or ions along the line via momentum transfer engendered by collision of the Cu atoms and/or ions with energetic, flowing electrons. The current flow also creates a thermal gradient along the conductor length which increases the mobility of the metal ions and/or atoms. As a consequence of the momentum transfer and the thermally enhanced mobility, metal (Cu) ions and/or atoms diffuse in the direction of the gradient, and metal (Cu) loss at the source end of the conductor eventually results in thinning of the conductor line. The electromigration effect can continue until the conductor line becomes so thin that it separates from the current input or forms an open circuit, resulting in circuit (i.e., semiconductor chip) failure. As this usually occurs over an extended period of operation, the failure is often seen by the end-user.
Therefore, as an additional step in the fabrication process, a treatment of the Cu and/or Cu alloy surface with a reducing agent such as ammonia (NH3) plasma is performed in order to reduce or eliminate any Cu oxide-containing layers formed on the Cu and/or Cu alloy surface as a result of the CMP process. Although the reducing agent treatment may advantageously remove any surface oxides, the elevated temperatures involved in the treatment may disadvantageously cause the formation of hillocks and other defects on the Cu and/or Cu alloy surface. Thus, the reducing agent treatment may undesirably increase the defect density on the surface of the Cu and/or Cu alloy pattern.
Thus, there exists a need for metallization process methodology which avoids the above-mentioned problems associated with oxide (particularly Cu oxide) formation on the metal surface, electromigration, and increased defect density, and which enables formation of metallization members, for example interconnect and routing lines (particularly of Cu or Cu-based alloys) having high reliability, high product yield, improved electromigration resistance, and high performance. In particular, there exists a need for eliminating the problems associated with electromigration and oxide layer formation resulting from CMP processing to form xe2x80x9cinlaidxe2x80x9d, xe2x80x9cdamascenexe2x80x9d-type Cu-based metallization patterns. Moreover, there exists a need for improved metallization processing technology which is fully compatible with conventional process flow, methodology, and throughput requirements in the manufacture of integrated circuit semiconductor devices and other devices requiring xe2x80x9cinlaidxe2x80x9d metallization patterns.
Embodiments of the invention pertain to a method of manufacturing an electrical or electronic device having highly reliable, electromigration-resistant metallization patterns.
Additional embodiments of the invention pertain to a method of manufacturing a semiconductor integrated circuit device having highly reliable, electromigration-resistant Cu-based metallization patterns.
Yet other embodiments of the invention pertain to a method of manufacturing xe2x80x9cinlaidxe2x80x9d, xe2x80x9cdamascenexe2x80x9d-type Cu-based metallization patterns having improved reliability, high conductivity, and improved electromigration resistance.
Yet other embodiments of the invention pertain to a semiconductor device comprising a substrate including at least one damascene-type metal feature inlaid in the upper, exposed surface of a layer of dielectric material overlying at least a portion of the substrate. The at least one metal feature comprises an alloy of a conductive metal and at least one alloying element such that under conditions wherein an oxide layer forms on the surface of the at least one metal feature, the at least one alloying element forms a more stable oxide layer on the surface of the metal feature than an oxide layer that would be formed on the surface of the metal feature in the absence of the diffused at least one alloying element. Thus a more stable oxide layer is formed on the surface of the metal feature which reduces electromigration of atoms and/or ions from the metal feature along the oxide layer.
In accordance with preferred embodiments, a substrate is provided which may include at least one damascene-type metal feature inlaid in the upper, exposed surface of a layer of dielectric material overlying at least a portion of the substrate, the at least one metal feature including an upper, exposed surface substantially co-planar with the upper surface of the layer of dielectric material. At least one layer comprising at least one alloying element for the metal feature may then be deposited on the exposed, upper surface of the at least one metal feature and on the upper surface of the layer of dielectric material.
The at least one alloying element may then be diffused within the at least one metal feature such that under conditions wherein an oxide layer forms on the surface of the at least one metal feature, the at least one alloying element forms a more stable oxide layer on the surface of the metal feature than an oxide layer that would be formed on the surface of the metal feature in the absence of the diffused at least one alloying element, thus reducing electromigration of atoms and/or ions from the metal feature along the oxide layer. Any remaining portion of the at least one alloying element which extends above the upper, exposed surface of the layer of dielectric material after diffusing the at least one alloying element within the at least one metal feature may then be removed.
In a preferred embodiment of the invention, the electrical device may comprise a semiconductor integrated circuit device and the substrate may comprise a semiconductor wafer of monocrystalline silicon (Si) or gallium arsenide (GaAs) having a major surface, with the dielectric layer being formed over at least a portion of the major surface, and the at least one damascene-type, inlaid metal feature may comprise a plurality of unalloyed Cu features for providing vias, interlevel metallization, and/or interconnection lines of at least one active device region or component formed on or within the semiconductor wafer.
The at least one alloying element may include, but is not limited to, at least one of tin (Sn), zirconium (Zr), magnesium (Mg), and palladium (Pd) and may form a stable oxide layer including, but not limited to, at least one of tin oxide (SnO), zirconium oxide (ZrO2), magnesium oxide (MgO), and palladium oxide (PdO2). The stable oxide layer reduces electromigration of Cu atoms and/or ions from the Cu features along the oxide layer. The at least one alloying element may be blanket-deposited by a physical vapor deposition (PVD) process and may be diffused within the at least one Cu feature by an annealing process. The remaining portion of the at least one layer may then be removed by a chemical-mechanical polishing process. A silicon nitride encapsulation layer may then be deposited over the at least one metal feature and the upper, exposed surface of the layer of dielectric material.